The present invention relates to a semiconductor integrated circuit device having a semiconductor memory device, and more particularly to a technology effective in application to a static RAM (random access memory) of a system in which data lines coupled with memory cells are precharged.
Memory cells in a MOS static RAM, for example, typically are constituted of static flip flop circuits, which are formed of a pair of drive MOSFETs with their gates and drains cross-connected, a load element, and a pair of transmission gate MOSFETs. The memory array includes, other than plural memory cells disposed as a matrix, plural pairs of complementary data lines, each pair thereof being coupled with input and output terminals of the corresponding memory cells.
A readout signal output from a selected memory cell is transmitted through a pair of the complementary data lines to be amplified by a sense amplifier circuit using, for example, a differential MOSFET arrangement.
Previously a multiplex apparatus has been developed in which plural digital channels are multiplexed in a single digital line and a static RAM is incorporated for performing high-speed transmission. In such a multiplex apparatus, the static RAM is used, for example, as a time-division switch. In such a case, the processing capacity of the multiplex apparatus is dependent on the access time of the incorporated static RAM. Therefore, as one of the methods to achieve the high speed functioning of such a static RAM thereby to improve the processing capacity of the multiplex apparatus, a half precharge method has been proposed in which the complementary data lines are charged to a voltage of approximately half the level of the source voltage Vcc.
Such a half precharge method is disclosed, for example, in U.S. patent applications Ser. No. 860411 by M. Uchida, Ser. No. 943063 by M. Uchida, and Ser. No. 60334 by A. Ito, of which the assignee is Hitachi, Ltd. the same as the assignee of the present application.
Referring to the aforesaid Ser. No. 860411, noninverted signal line D0 is precharged to the level of the source voltage Vcc and inverted signal line D0 is precharged to ground potential GND of the circuit. Then, by shorting (equalizing) the noninverted signal line D0 and the inverted signal line D0, both the signal lines are brought to a level of approximately 1/2 Vcc.
Referring to Ser. No. 943063, noninverted signal line D0 and inverted signal line D0 are also brought to a level of approximately 1/2 Vcc by a similar precharge method to the above.
Referring to Ser. No. 60334, one set of complementary data lines D0, D0 are precharged to a level of the source voltage Vcc and the other set of complementary data lines D1, D1 are precharged to ground potential level of the circuit. Then, the former complementary data lines D0, D0 and the latter complementary data lines D1, D1 are shorted (equalized) and thereby both complementary data lines are brought to a level of approximately 1/2 Vcc. In this precharge method, a difference exists in the level between one and the other of the two sets of complementary data lines to be formed into one pair in the early stage. However, the noninverted signal lines and the inverted signal lines of the complementary data lines coupled with the input and output nodes of a memory cell are brought to the same level by the equalizing.